`include "chunjun_define.sv" 
`include "chunjun_lib_define.sv" 
 
//================================================================================================
// File Name   : vtcu_bank_judge.sv
// Create Time : Thu Dec 26 16:33:34 2024
// Description :
// 
//================================================================================================

module vtcu_bank_judge #(parameter  BANK_N      = 2,
                                    BANK_DATA_W = 32,
                                    // BANK_ADDR_W = 13,
                                    IN_ADDR_W   = 32,
                                    MODE        = 2'b00
) (
input   logic [IN_ADDR_W-1:0]                      i_addr          ,
output  logic [BANK_N-1:0]                         o_bank_sel_oh   
// output  logic [BANK_ADDR_W-1:0]                     o_addr          
);
genvar i,j;
 
localparam CHECK_LSB    = $clog2(BANK_DATA_W/8); //2
localparam CHECK_WIDTH  = $clog2(BANK_N);        //1
localparam CHECK_MSB    = CHECK_LSB + CHECK_WIDTH - 1; //2
generate
if(MODE==2'b00) begin : BANK_MODE0_GEN
    for(i=0; i<BANK_N; i=i+1)begin: GEN_BANK_JUDGE
        assign o_bank_sel_oh[i] = (i_addr[CHECK_MSB:CHECK_LSB] == i);
    end
    // assign o_addr = i_addr[(CHECK_MSB+1) +: BANK_ADDR_W];
end
else begin
    assign o_bank_sel_oh = 'h0;
    // assign o_addr = 'h0;
end
endgenerate
endmodule
`include "chunjun_undefine.sv" 
